/*
 * Ingenic CU1830-Neo configuration
 *
 * Copyright (c) 2017  Ingenic Semiconductor Co.,Ltd
 * Author: Zoro <ykli@ingenic.cn>
 * Based on: include/configs/urboard.h
 *           Written by Paul Burton <paul.burton@imgtec.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_CU1830_NEO_H__
#define __CONFIG_CU1830_NEO_H__

/**
 * Basic configuration(SOC, Cache, UART, DDR).
 */
#define CONFIG_SYS_EXTAL			24000000	/* EXTAL freq: 24 MHz */
#define CONFIG_SYS_HZ_CLOCK			1500000		/* incrementer freq */
#define CONFIG_SYS_MIPS_TIMER_FREQ	1500000000

/**
 * Command configuration.
 */
#define CONFIG_CMD_EXT4 		/* ext4 support			*/
#define CONFIG_CMD_SETGETDCR	/* DCR support on 4xx		*/
#define CONFIG_CMD_GETTIME
#define CONFIG_CMD_UNZIP        /* unzip from memory to memory  */
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING

/* NS16550-ish UARTs, uart[0134] are accessible */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_EXTAL
#define CONFIG_SYS_NS16550_COM1		0xb0030000 /* uart0 */
#define CONFIG_SYS_NS16550_COM2		0xb0031000 /* uart1 */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_CONSOLE_MUX
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE \
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200, 230400 }


/*#define CONFIG_SPL_MMC_SUPPORT*/

/**
 * Drivers configuration.
 */
/* MMC */
#ifdef CONFIG_JZ_MMC_MSC0
	#define CONFIG_CMD_MMC			/* MMC/SD support*/
	#define CONFIG_JZ_MMC_SPLMSC	0
#endif  /* JZ_MMC_MSC0 */

/* SFC */
#ifdef CONFIG_MTD_SFCNOR
	#define CONFIG_CMD_SFC_NOR
	#define CONFIG_JZ_SFC
	#define CONFIG_JZ_SFC_NOR
	#define CONFIG_SFC_QUAD
	#define CONFIG_SFC_NOR_RATE					150000000
	#define CONFIG_SPIFLASH_PART_OFFSET         (CONFIG_SPL_MAX_SIZE)
	#define CONFIG_SPI_NORFLASH_PART_OFFSET     (CONFIG_SPIFLASH_PART_OFFSET + ((size_t)&((struct burner_params*)0)->norflash_partitions))
	#define CONFIG_NOR_MAJOR_VERSION_NUMBER     1
	#define CONFIG_NOR_MINOR_VERSION_NUMBER     0
	#define CONFIG_NOR_REVERSION_NUMBER         0
	#define CONFIG_NOR_VERSION     (CONFIG_NOR_MAJOR_VERSION_NUMBER | (CONFIG_NOR_MINOR_VERSION_NUMBER << 8) | (CONFIG_NOR_REVERSION_NUMBER <<16))
	#define CONFIG_ENV_IS_IN_SFC_NOR
#endif /*MTD_SFCNOR*/

/* GMAC */
#define GMAC_PHY_MII	1
#define GMAC_PHY_RMII	2
#define GMAC_PHY_GMII	3
#define GMAC_PHY_RGMII	4
#define CONFIG_NET_GMAC_PHY_MODE GMAC_PHY_RMII

#define PHY_TYPE_DM9161		1
#define PHY_TYPE_88E1111	2
#define PHY_TYPE_8710A		3
#define PHY_TYPE_IP101G		4

#define CONFIG_NET_PHY_TYPE   PHY_TYPE_IP101G

#define CONFIG_NET_X1830
#define CONFIG_SET_ETHADDR

#define CONFIG_GPIO_IP101G_RESET		GPIO_PB(28)
#define CONFIG_GPIO_IP101G_RESET_ENLEVEL	0

/* DEBUG ETHERNET */
#define CONFIG_SERVERIP     192.168.10.94
#define CONFIG_IPADDR       192.168.10.33
#define CONFIG_GATEWAYIP    192.168.10.1
#define CONFIG_NETMASK      255.255.255.0
#define CONFIG_ETHADDR      00:11:22:33:44:55

/*pmu slp pin*/
#define CONFIG_REGULATOR
#ifdef  CONFIG_REGULATOR
	#define CONFIG_JZ_PMU_SLP_OUTPUT1
	#define CONFIG_INGENIC_SOFT_I2C
	#define CONFIG_PMU_EA3056
	#define CONFIG_EA3056_I2C_SCL	GPIO_PC(28)
	#define CONFIG_EA3056_I2C_SDA	GPIO_PC(27)
	#define CONFIG_SOFT_I2C_READ_REPEATED_START
#endif

/**
 * Miscellaneous configurable options
 */
#define CONFIG_EXT4_WRITE
#define CONFIG_PARTITION_UUIDS

#define CONFIG_SHA1
#define CONFIG_LZO
#define CONFIG_BZIP2
#define CONFIG_RBTREE
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_FLASH_BASE	0 /* init flash_base as 0 */
#define CONFIG_SYS_BOOTM_LEN	(128 << 20)
#define CONFIG_ENV_OVERWRITE
#define CONFIG_MISC_INIT_R	1
#define CONFIG_SYS_MAXARGS 	16

#if defined(CONFIG_SPL_SFC_NOR)
	#define CONFIG_SPL_SFC_SUPPORT
#endif

#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)

#define CONFIG_SYS_MONITOR_LEN		((256 * 1024) - CONFIG_SPL_PAD_TO)
#define CONFIG_SYS_MALLOC_LEN		(32 * 1024 * 1024)
#define CONFIG_SYS_BOOTPARAMS_LEN	(128 * 1024)

#define CONFIG_SYS_SDRAM_BASE		0x80000000 /* cached (KSEG0) address */
#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
#define CONFIG_SYS_LOAD_ADDR		0x88000000
#define CONFIG_SYS_MEMTEST_START	0x80000000
#define CONFIG_SYS_MEMTEST_END		0x84000000

#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE

/**
 * Environment
 */
#if defined(CONFIG_ENV_IS_IN_MMC)
	#define CONFIG_SYS_MMC_ENV_DEV		0
	#define CONFIG_ENV_SIZE			(16 * 1024)
	#undef CONFIG_SYS_MONITOR_LEN
	#define CONFIG_SYS_MONITOR_LEN          ((512 * 1024) - (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) - CONFIG_ENV_SIZE)
	#define CONFIG_ENV_OFFSET		(CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#elif defined(CONFIG_ENV_IS_IN_SFC_NOR)
	#define CONFIG_ENV_SIZE			(16 * 1024)
	#undef CONFIG_SYS_MONITOR_LEN
	#define CONFIG_SYS_MONITOR_LEN		((512 * 1024) - CONFIG_UBOOT_OFFSET - CONFIG_ENV_SIZE)
	#define CONFIG_ENV_OFFSET		(CONFIG_SYS_MONITOR_LEN + CONFIG_UBOOT_OFFSET)
#else
	#define CONFIG_ENV_IS_NOWHERE
	#define CONFIG_ENV_SIZE			(512)
#endif

/**
 * SPL configuration
 */
#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_REGULATOR_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#ifdef CONFIG_SPL_MMC_SUPPORT
  #define CONFIG_SPL_MAX_SIZE		26624
  #define CONFIG_SPL_PAD_TO	        CONFIG_SPL_MAX_SIZE
#elif defined(CONFIG_SPL_SFC_SUPPORT)
  #define CONFIG_SPI_SPL_CHECK
  #define CONFIG_SPL_PAD_TO		27648
  #define CONFIG_SPL_MAX_SIZE		(26 * 1024)
  #define CONFIG_UBOOT_OFFSET           CONFIG_SPL_PAD_TO
  #define CONFIG_SPL_VERSION            1
#endif	/*CONFIG_SPL_NOR_SUPPORT*/

#define CONFIG_SPL_STACK		0x80008000 /* only max. 2KB spare! */
#define CONFIG_SPL_BSS_START_ADDR	0x80004000
#define CONFIG_SPL_BSS_MAX_SIZE		0x00002000 /* 512KB, arbitrary */

#define CONFIG_SPL_START_S_PATH		"arch/mips/mach-jz47xx"

#define CONFIG_GPT_TABLE_PATH	"board/$(BOARDDIR)"

#endif /*__CONFIG_CU1830_NEO_H__*/
